The present invention relates to a semiconductor process and in particular to fabrication of a semiconductor device using a partially recessed hard mask.
The increasing demand for highly integrated and high-performance semiconductor devices has fueled the need for advances in integrated circuit manufacturing technology. To produce an integrated circuit with high integration density, semiconductor device and interconnect sizes must be reduced. Lithography and etching form trenches and contact holes in the dielectric layer prior to formation of the interconnects. Thereafter, the trenches and contact holes are filled with a metal layer, followed by polishing to complete the fabrication. This is a typical damascene process in semiconductor manufacturing technology. In a common etching technique used to form openings, such as trenches or contact holes, in a target layer on a substrate, a photoresist pattern is formed on the target layer serving as an etch mask. Since the thickness of the photoresist pattern can dictate the etching rate, the photoresist pattern must be thick if the contact holes are to be very small.
A photoresist layer having a thickness of 3000 Å or more, however, is not sensitive to the light used for lithography. That is, it is difficult to form a contact hole with a small critical dimension using a photoresist layer as an etch mask. Accordingly, the fabrication of a contact hole with small critical dimension using a polysilicon layer as an etch mask has been widely employed.
FIG. 1 is a cross-section of a conventional semiconductor device fabricated using a single polysilicon hard mask. The semiconductor device comprises a substrate 100, an interlayer dielectric (ILD) layer 112, a polysilicon hard mask 114, a barrier layer 116, and a metal layer 118. The substrate 100 comprises a device region 10 and an alignment region 20, in which the device region 10 has a plurality of gate structures 107 formed thereon and the alignment region 20 has an opening 101 formed in the substrate 100 serving as an alignment mark (AM). The gate structure 107 comprises a gate dielectric layer 102, a gate electrode 104, and a gate spacer 106. The ILD layer 112 overlies the substrate 100, with the portion thereof over the device region 10 comprising a bit line contact hole (CB) 113a, a gate contact hole (CG) 113b, and a substrate contact hole (CS) 113c therein. The portion of ILD layer 112 on the alignment region 20 has an opening therein to expose the opening 101. The polysilicon hard mask 114 is disposed on the ILD layer 112 and the portion thereof over the device region 10 has a plurality of holes to expose the bit line contact hole 113a, the gate contact hole 113b, and the substrate contact hole 113c and the portion over the alignment region 20 has an opening therein to expose the opening (alignment mark) 101. The barrier layer 116 comprising titanium nitride is conformably disposed on the polysilicon hard mask 114 and the inner surfaces of the contact holes 113a, 113b, and 113c and the opening 101. The metal layer 118, such as a tungsten layer, is conformably formed on the barrier layer 116 and the opening 101 and fills the contact holes 113a, 113b, and 113c. 
During the fabrication of the semiconductor device, the alignment mark 101 on the alignment region 20 may fail due to light strongly reflected from the thicker polysilicon hard mask 114. That is, it is difficult to define the contact holes 113a, 113b, and 113c during lithography. In order to solve this problem, the polysilicon hard mask 114 over the alignment mark 101 must be removed prior to definition of the contact holes 113a, 113b, and 113c. As a result, a deeper and wider opening is formed by removing the ILD layer 112 over the alignment mark 101 during definition of the contact holes 113a, 113b, and 113c. As the subsequent metal layer 118 is filled for the fabrication of contact plugs, the deeper and wider opening cannot be completely filled with the metal layer 118. The metal layer 118, however, is conformably formed on the inner surface of the opening. A dishing effect thus occurs during planarization by chemical mechanical polishing (CMP). As a result, the metal layer 118 adjacent to the alignment mark 118 is disconnected, as depicted by the arrows 119 shown in FIG. 1, thus reducing device reliability.